Conventional semiconductor devices, such as the one shown in FIG. 1, include a refractory metal deposited over all exposed upper surface features of a silicon substrate 101, preferably by means of physical vapor deposition (PVD). The most common refractory metal employed is nickel, which forms a very low resistivity silicide with silicon and does not consume as much Si as other silicides commonly employed. NiSi has a great resistance to etchants which are used to etch silicon oxide, a common insulating material used in semiconductor devices.
The refractory metal can be sputtered by DC magnetron sputtering in an ultra-high vacuum, multi-chamber system. Tile formation of an MOS transistor requires the formation of a gate structure 103 and source/drain junctions 105. The gate electrode 103 typically is formed by depositing a layer of heavily doped polysilicon 103a on a metal oxide insulating layer 103b and etching the layers to pattern the electrode. Sidewall spacers 107 are deposited on the opposing surfaces of the patterned gate electrode with oxide liner 109 between spacer 107 and both gate electrode 103 and substrate 101. The sidewall spacers 107 comprise silicon oxide, silicon nitride or silicon oxynitride.
Generally, in forming the MOS transistor, the refractory metal is deposited after etching the gate electrode 103 and after forming the source/drain junction 105, as illustrated in FIG. 1. After deposition, the refractory metal layer blankets the top surface of the gate electrode 103, sidewall spacers 107, oxide liners 109, and source/drain regions 105. As a result of thermal processing, e.g., a rapid thermal annealing (RTA) process, performed in an inert or reducing atmosphere, the refractory metal reacts with underlying silicon to form electrically conductive silicide layer portions 111 on the top surface of the polysilicon gate electrode 103 and on the exposed surfaces of the substrate where source and drain regions 105 are formed. Unreacted portions of the refractory metal layer, e.g., on the silicon oxide, nitride or oxynitride sidewall spacers 107 and the silicon oxide liner 109 are then removed, as by a wet etching process selective to the metal silicide portions 111.
Substrates based on “strained silicon” have attracted interest as a semiconductor material which provides increased speeds of electron and hole flow therethrough, thereby permitting fabrication of semiconductor devices with higher operating speeds, enhanced performance characteristics, and lower power consumption. A layer 101a of silicon-germanium (Si—Ge) is formed on a suitable crystalline substrate, e.g., a Si wafer or a silicon-on-insulator (SOI) wafer 101b. The Si—Ge layer has a greater lattice constant (spacing of Si and Ge atoms therein) relative to the underlying Si. As a consequence, the Si—Ge layer has a compressive strain. Electrons in such compressively strained layers have greater mobility than in conventional Si layers with smaller inter-atom spacings, i.e., there is less resistance to electron flow. For example, electron flow may be up to about 70% faster compared to electron flow in conventional Si. Transistors and IC devices formed with such strained Si layers can exhibit operating speeds up to about 35% faster than those of equivalent devices formed with conventional Si, without necessity for reduction in transistor size. Conventional practices based on strained silicon technology also involve epitaxially growing a relaxed silicon layer on a tensilely stressed silicon layer which is subsequently doped to form relaxed source/drain regions in the relaxed silicon layer.
Conventional semiconductor devices typically comprise a plurality of active devices in or on a common semiconductor substrate, e.g., CMOS devices comprising at least a pair of PMOS and NMOS transistors in spaced adjacency. The mobility of electrons is faster than the mobility of holes in conventional bulk silicon substrates. Accordingly, in conventional CMOS transistors, the drive current of the PMOS transistor is less than the drive current of the NMOS transistor creating an imbalance. This imbalance is exacerbated in CMOS transistors fabricated on or within a tensilely stressed active device area formed in a strained lattice semiconductor substrate, e.g., strained Si—Ge on Si, because the increase in electron mobility is greater than the increase in hole mobility.
Channel carrier mobility of transistors based on strained Si substrates can be increased by applying a stress thereto. In forming P-channel transistors, channel carrier mobility is enhanced by applying a stressed dielectric layer exhibiting high compressive stress for increasing electron mobility. In N-channel transistors, channel carrier mobility is significantly increased by applying a stressed layer exhibiting high tensile stress for increasing hole mobility. Stressed dielectric layers, called stress liners, are applied to transistors wherein the source/drain regions are formed within the strained Si layer, and to transistors having relaxed source/drain regions formed on strained Si layers. The stress liner may comprise silicon carbide, silicon nitride or silicon oxynitride, and may be deposited by plasma enhanced chemical vapor deposition (PECVD) at a thickness of about 200 Å to about 1000 Å. Conventional PECVD conditions may be employed for deposition of a highly compressive layer or highly tensile dielectric layer. In depositing a stress liner exhibiting high compressive stress, both high frequency and low frequency power are applied. When depositing a stressed dielectric layer exhibiting high tensile stress, the low frequency power is significantly reduced.
Because the stress liners differ for P-channel and N-channel transistors, the stressed dielectric layers are typically patterned by reactive ion etching, which involves physically bombarding the surfaces to subtractively remove material. This etching process involves an “overetch” in order to clear the residue left behind. It is during this overetch process that the underlying NiSi layers are damaged, causing degradation of the NiSi. The degradation can be morphological, wherein mouse bites or missing NiSi is observed, as illustrated in FIG. 1 at 113a-113f, or electrical, wherein the resistivity is increased. Either or both types of degradation ultimately result in poor device parameters such as higher sheet resistance and external resistance.
A need therefore exists for methodology enabling fabrication of semiconductor devices comprising transistors with degradation resistant NiSi layers and for the resulting improved semiconductor devices having reduced resistance and improved performance.